Semiconductor Engineering

A Test Generation Procedure Targeting Subcircuits With High Susceptibilities To Aging (Purdue University)

A technical paper titled “Test Generation for Subcircuits with High Functional Switching Activities” was published by Irith Pomeranz at Purdue University. Abstract “Chip aging results in defects that ...
EDN

Scan-based transition-fault test can do job

Delay-inducing defects are causing increasing concern in the semiconductor industry today, particularly at the leading-edge 130- and 90- nanometer nodes. To effectively test for such defects, the ...
Business Wire

Astronics Test Systems Introduces New Wire Fault Test Solution

EAST AURORA, N.Y.--(BUSINESS WIRE)--Astronics Corporation (NASDAQ:ATRO), a leading provider of advanced technologies for the global aerospace, defense and semiconductor industries, announced today ...
Semiconductor Engineering

Aging Aware Steepening Metric for the Fault Coverage of a Test Set (Purdue Univ.)

A new technical paper titled “Aging Aware Steepening of the Fault Coverage Curve of a Scan Based Transition Fault Test Set” was published by researchers at Purdue University. “Chip aging may result in ...
Electronic Design

Debugging Low Test-Coverage Situations

Scan is a structured test approach in which the overall function of an integrated circuit (IC) is broken into smaller structures and tested individually. Every state element (D flip-flop or latch) is ...
Electronic Design

Reduce Test/Diagnosis Cost with Optimized Scan-Pattern Ordering

Download this article in PDF format. Finding the right balance among test cost, test quality, and data collection for running diagnosis requires consideration of several competing factors. Luckily ...